1. Field of the Invention
The invention is directed to methods and apparatus for efficiently accessing electronic memory devices.
2. Description of Related Art
With the constant increase in speed of processors and complexity of computer applications, there is an ever present need in today's computer systems to reduce any unnecessary processing delays. One technique that is commonly used for reducing the time involved in accessing semiconductor memory arrays is known as "burst access." During a burst access "read" operation, a single address is provided to a memory device on its address bus. The data word stored in the memory device at the given address is then output on a data bus. Subsequently, a predetermined number of additional data words which may, for example, be stored in the memory device at sequential addresses, are then also automatically read out in successive clock cycles over the data bus without any additional address signals being sent over the address bus. The problem inherent in such a burst scheme is that the access of the memory device is still performed one location at a time and the delay in accessing the sequential data, though improved, can still be substantial.
An alternative "burst access" scheme is also known which involves the use of extra wide data buses to increase the data rate (i.e., "bandwidth") of the memory device access. U.S. Pat. No. 5,561,636, for example, discloses a Synchronous Dynamic Random Access Memory (SDRAM) architecture that uses a wider on-chip data bus (64-bit) than its off-chip I/O bus (32-chip). The wider on-chip data bus allows simultaneous transfer (known as one form of "prefetching") of data from the memory array with sequential transfer of the data to the I/O bus devices as needed. U.S. Pat. No. 5,546,346, discloses another SDRAM architecture that utilizes a multiplexer/selector between the memory array and an external interface to facilitate the sequential transfer of data to an external device. See also U.S. Pat. No. 5,673,414 (simultaneous prefetch of 16-byte packets of contiguous data stored in a buffer and read by I/O device in 1, 2 or 4 byte sections); and U.S. Pat. No. 5,390,149 (M data bits are transferred in parallel from memory array and one-out-of-M selection of these bits is output from an internal multiplexer in response to address control signals).
A significant drawback of the burst access scheme using an extra wide data bus is the large size of the buses required to transfer data from the array to the input/output lines. Such buses can consume large amounts of die area. Where multiple memory devices are needed on a single integrated circuit, much of the die area will be consumed by the large buses required for each memory unit.